a) Field of the Invention
The present invention relates to a semiconductor device and its manufacturing method, and more particularly to a semiconductor device having insulated gate type field effect transistors (IGFET) fabricated at a high integration.
b) Description of the Related Art
As patterns of large scale integration (LSI) circuits are becoming finer, it is desired to improve a pattern transfer precision. Anisotropic dry etching such as reactive ion etching (RIE) and electron cyclotron resonance (ECR) plasma etching is widely used so as to reliably transfer a mask pattern on a layer such as a wiring layer to be processed. Such anisotropic dry etching uses plasma or ions.
A plasma process is likely to produce an electrical stress such as a damage caused by non-uniformity of plasma (refer to J. Appl. Phys. 72 (1992) pp. 4865-4872). As patterns are becoming finer, the gate insulating film of an insulated gate type field effect transistor (IGFET) is becoming thinner. There are many gate insulating films which have a thickness of 10 nm or less and are susceptible to influences and damages by an electrical stress. For example, if a Fowler-Nordheim (FN) tunnel current flows through a gate insulating film, defects corresponding in amount to an integrated current flow are formed so that the threshold voltage changes. If a dielectric breakdown occurs, the gate electrode and semiconductor substrate are short-circuited.
A gate oxide film having a thickness of 10 nm is full of danger of breakdown when a voltage of 10 to 15 V or higher is applied. In a plasma atmosphere, a potential Vdc at the surface of a layer to be processed reaches 100 to 1000 V. It is not easy to set a uniformity of potential distribution 5% or less.
Therefore, there is a high danger of breaking a gate insulating film during a plasma process. This danger is present not only when patterning a wiring layer, but also when opening a contact hole or when cleaning a contact hole by plasma sputtering.
Conventionally, such a damage phenomenon has been considered to be resulted from non-uniformity of the electric or magnetic property of plasma. Therefore, as a means of eliminating damages, it has been endeavored to generate and use uniform plasma.
More specifically, it has been proposed to uniformize a bias voltage by providing a uniform plasma potential and a position independence of an electron mobility. For example, in a configuration that magnetic fluxes traverse over the surface of a layer to be processed, it has been proposed not to change the vertical components of a magnetic field between the surfaces of a central area and a peripheral area of a layer to be processed.
The present inventors have found that damages may be generated depending upon a type of patterns to be processed, even if the non-uniformity of plasma is improved.
It is an object of the present invention to provide a semiconductor device and its manufacturing method, capable of eliminating damages even if fine patterns are processed.
According to one aspect of the present invention, there is provided a method of manufacturing a semiconductor device containing insulated gate type field effect transistors, including the steps of: forming a gate insulating film and an electrode layer on a semiconductor substrate; patterning the electrode layer to form a gate electrode layer having a predetermined area and facing the semiconductor substrate with the gate insulating film being interposed therebetween; forming an interlayer insulating film covering the gate electrode layer; forming a wiring layer connected to the gate electrode layer on the interlayer insulating film; forming a conductive material layer on the wiring layer; coating a resist layer on the conductive material layer; patterning the resist layer to form a resist mask forming a wiring pattern having an antenna ratio of about ten times or more relative to the predetermined area of the gate electrode layer facing the semiconductor substrate; first plasma-etching at least the conductive material layer by using the resist mask as an etching mask; removing the resist mask after the first plasma-etching step; and after removing the resist mask, second plasma-etching at least part of the wiring layer connected to the gate electrode layer.
According to another aspect of the present invention, there is provided a method of manufacturing a semiconductor device having a conductive film pattern with a pattern space of 1 xcexcm or less, including the steps of: forming an electrode layer on part of the surface of a semiconductor substrate, with a thin insulating film being interposed therebetween; forming an interlayer insulating film on the electrode layer, the interlayer insulating film being formed with a contact hole; forming a conductive film on the interlayer insulating film; forming an insulating material mask layer on the conductive film; coating a resist layer on the insulating material mask layer; patterning the resist layer; patterning the insulating material mask layer by using the resist layer as an etching mask; removing the resist layer; and plasma-etching and patterning the conductive layer by using the insulating material mask layer as an etching mask, wherein the thickness of the insulating material mask layer is set to a half or less of a minimum pattern space.
According to a further aspect of the present invention, there is provided a method of manufacturing a semiconductor device, wherein in etching a wiring layer connected to an insulated gate of an insulated gate type field effect transistor or an insulating layer on the wiring layer by using plasma having uniform characteristics and exposed on the surface of a material to be processed, an RF bias having a frequency of 1 MHz or lower is applied to the material to be processed so as to make the amounts of ions and electrons incident generally in the vertical direction upon the surface of the wiring layer, generally equal to each other.
According to a still further aspect of the present invention, there is provided a method of manufacturing a semiconductor device for forming a first wiring layer and a second wiring layer at the same time, the first wiring layer being connected to a gate electrode on a gate insulating film formed on a semiconductor region of a first conductivity type, and the second wiring layer being connected to the semiconductor region, wherein in patterning the first and second wiring layers, a third wiring layer electrically separated from and placed between the first and second wiring layers is left unetched.
In etching a conductive pattern connected to a gate electrode on a thin insulating film and having a high antenna ratio relative to an intrinsic gate area, damages are formed in the gate structure even if uniform plasma is used. However, if the mask of plasma etching is made conductive, it is possible to avoid damages in the gate structure. If a mask is not conductive, an imbalance between positive and negative charges incident upon a conductive layer under the mask to be processed, results in a charge-up of the conductive layer to be processed. If a mask is conductive, it is conceivable that it is not necessary to balance positive and negative barges only by the conductive layer under the mask, but positive arid negative charges are balanced by a combination of the mask and the conductive layer to be processed.
If an antenna ratio is 10 or higher and a charge-up occurs once, a current amplified about 10 times or more flow through the region having a low insulating strength. Therefore, the characteristics of a semiconductor device are easily changed. A balanced charge eliminates a tunnel current and allows a semiconductor device having a desired performance to be manufactured.
If the area of side walls of a non-conductive mask is negligibly small, damages can be avoided. The reason for this may be a small absolute value of negative charges incident upon the side walls of a non-conductive mask. Specifically, damages can be effectively avoided if the thickness of a mask is a half or less of a minimum pattern space.
A conventional uniform plasma can be considered as having the same amounts of positive and negative charges incident upon a flat surface. However, if the incident directions are taken into consideration, uniformity cannot be ensured. Accordingly, it is conceivable that there are irregularities if only the charges incident in the vertical direction through an opening in a non-conductive mask are taken into consideration.
If these irregularities are eliminated, positive and negative charges can be balanced and damages can be avoided. In order to control a balance between positive and negative charges incident in the vertical direction from plasma to the surface of a material to be processed, it is effective that the frequency of an RF bias is set to 1 MHz or lower. It is also effective to apply a divergent magnetic field and an auxiliary mirror magnetic field for balancing charges incident in the vertical direction upon the surface of a material to be processed.
It is possible to avoid damages to be caused by plasma while etching a dense wiring pattern, forming a contact hole, or cleaning a contact hole.